A phase detector (PD) is widely used for receiving a data signal and an output clock signal, and comparing the data signal with the output clock signal, thereby generating a judging signal. For example, the use of the phase detector is common in phase locked loop (PLL) circuits, for precisely controlling the clock and frequency. In addition, the PLL circuit is important for clock and data recovery (CDR) circuits.
FIG. 1A is a schematic diagram illustrating a correction strategy of a linear phase detector. For the linear phase detector, as the phase difference φ increases, the phase-correcting amount Δφ increases in a direct proportion. That is, the phase difference φ and the phase-correcting amount Δφ are in a linear relationship. If the phase difference φ is positive, the phase-correcting amount Δφ is subtracted from the original phase. Whereas, if the phase difference φ is negative, the phase-correcting amount Δφ is added to the original phase.
FIG. 1B is a schematic diagram illustrating a correction strategy of a bang-bang phase detector. The bang-bang phase detector is a non-linear phase detector. After the phase difference is detected, depending on the positive or negative feature of the phase difference, a constant phase-correcting amount Δφ is subtracted from or added to the original phase. If any phase difference still exists after the correction step, the similar correction steps are repeated done to successively correct the original difference by the constant phase-correcting amount Δφ. For example, assuming that the phase difference φ between the data signal and the clock signal inputted into the phase detector is positive, the constant phase-correcting amount Δφ is subtracted from the original phase, and thus a judging signal Vdown is outputted from the bang-bang phase detector. Whereas, if the phase difference φ is negative, the constant phase-correcting amount Δφ is added to the original phase, and thus a judging signal Vup is outputted from the bang-bang phase detector.
From the above discussions, it is found that the correcting procedure of the linear phase detector may be stopped because the error is nearly negligible. On the other hand, since the sampling values acquired by the bang-bang phase detector are usually unequal, the correcting procedure of the bang-bang phase detector may be continuously performed because of the existence of the phase difference φ. In addition, even if the corrected value is very close to the ideal value, the corrected value may swing up and down with respect to the ideal value. Due to these characteristics, the bang-bang phase detector is also referred as a binary phase detector. Since the bang-bang phase detector does not need to calculate the tuning range according to the magnitude of the phase difference φ and the tuning speed of the bang-bang phase detector is faster than the linear phase detector, the bang-bang phase detector is employed in high-speed data transmission.
FIG. 2 is a schematic circuit diagram illustrating a clock and data recovery circuit using a bang-bang phase detector according to the prior art. As shown in FIG. 2, the clock and data recovery circuit comprises a bang-bang phase detector 101, a charge pump (CP) 103, a loop filter (LF) 105 and a voltage-controlled oscillator (VCO) 107. By the bang-bang phase detector 101, a judging signal (Vup, Vdown) is acquired. The judging signal is converted into control voltage by the charge pump (CP) 103 and the loop filter (LF) 105. According to the control voltage, the voltage-controlled oscillator adjusts the phase of an output clock signal.
Please refer to FIG. 2 again. The charge pump 103 comprises a first current source 1031, a second current source 1032, a first switch 1033 and a second switch 1034. The first current source 1031 is connected to a high-level voltage for providing a first switching current. The second current source 1032 is connected to a low-level voltage for providing a second switching current. The first switch 1033 is interconnected between the first current source 1031 and the loop filter 105. According to the judging signal outputted from the bang-bang phase detector 101, the first switch 1033 is conducted or shut off to determine whether the first switching current is outputted or not. The second switch 1034 is interconnected between the second current source 1032 and the loop filter 105. Similarly, according to the judging signal outputted from the bang-bang phase detector 101, the second switch 1034 is conducted or shut off to determine whether the second switching current is outputted or not. As such, a switching signal indicative of the combination of the first switching current and the second switching current will be transmitted to the back-end circuit.
The switching signal outputted from the charge pump 103 is generated according to the judging signal (Vup, Vdown). According to the switching signal, a control voltage VLF at a control node of the loop filter 105 is adjusted. According to the control voltage VLF, the output oscillation feature of the voltage-controlled oscillator 107 is adjusted. For example, in a case that the judging signal (Vup, Vdown)=(0, 0) is transmitted from the bang-bang phase detector 101 to the charge pump 103, the first switch 1033 and the second switch 1034 of the charge pump 103 are both shut off, and thus the control voltage VLF to be transmitted to the voltage-controlled oscillator 107 is kept unchanged. Whereas, in response to the judging signal (Vup, Vdown)=(0, 1), the second switch 1034 is conducted and the second switching current is generated. Due to the second switching current, an integral capacitor C1 of the loop filter 105 begins to discharge, and thus the magnitude of the control voltage VLF decreases. Whereas, in response to the judging signal (Vup, Vdown)=(1, 0), the first switch 1033 is conducted and the first switching current is generated. Since the integral capacitor C1 of the loop filter 105 is charged by the first switching current, the magnitude of the control voltage VLF increases. Moreover, in response to the judging signal (Vup, Vdown)=(1, 1), the first switch 1033 and the second switch 1034 are both conducted, and thus the first switching current and the second switching current are generated. Since the first switching current and the second switching current flow toward the low-level voltage side, neither a charging operation nor a discharging operation on the loop filter 105 is performed.
From the above discussions, it is found that the actions of the first switch 1033 and the second switch 1034 of the charge pump 103 affect the operations of the loop filter 105 and the voltage-controlled oscillator 107. That is, after the charging operation on the loop filter 105 is stopped by controlling on/off statuses of the switches 1033 and 1034, the charges accumulated in the integral capacitor C1 of the loop filter 105 still have influences on the voltage inputted into the voltage-controlled oscillator 107. On the other hand, since the resistor R of the loop filter 105 does not have the memory effect, the voltage inputted into the voltage-controlled oscillator 107 is not affected by the resistor R. In other words, the resistor R is able to respond to the instantaneous actions of the switches without adversely affecting voltage inputted into the voltage-controlled oscillator 107.
That is, the resistor R and the integral capacitor C1 of the loop filter 105 affect the performance of the instantaneous response and the sustained response, respectively. Generally, the resistor R is suitable to instantaneous phase adjustment, but the integral capacitor C1 is suitable to frequency adjustment. However, because of the following reasons, the performance of the architecture of the clock and data recovery circuit as shown FIG. 2 is unsatisfied in high-speed applications.
Firstly, since the resistor R and the integral capacitor C1 are included in the loop filter 105, the high-speed phase control feature and the low-speed frequency control feature of the resistor R and the integral capacitor C1 should be taken into consideration when designing the loop filter 105. In addition, when the clock and data recovery circuit is used in high-speed applications, the circuitry of charge pump 103 should be correspondingly changed to comply with the back-end circuit. That is, the complexity of designing the charge pump 103 increases.
Secondly, the loop stability is adversely affected by a parasitic capacitor Cp. As shown in FIG. 2, the parasitic capacitor Cp gives rise to third-order effects because the original second-order loop becomes a third-order loop (having an additional pole). The third-order effects may degrade the loop stability and make the loop design difficult, particularly at high frequencies. (See, Wang, Shoujun, etc, “Design considerations for 2nd-order and 3rd-order bang-bang CDR loops, FIG. 5” 2005 IEEE Custom Integrated Circuits Conference (CICC 2005), San Jose, Calif., Sep. 18-21, 2005).
Moreover, for eliminating the influence of noise, the main circuit is usually equipped with some decoupling capacitors to filter off high-frequency noise. Like the parasitic capacitor Cp, the uses of these decoupling capacitors may give rise to third-order effects to slow down the response speed.
From the above discussions, the loop filter 105 consisting of the resistor R and the integral capacitor C1 may restrict the applications of the clock and data recovery circuit at high frequencies.